The present invention relates to a non-volatile flash memory (“NVM”) semiconductor device which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. More particularly, the invention relates to the structure of a NVM semiconductor device having two-bits per cell that are typically employed in memory arrays such as virtual ground (VG) arrays or not-and-gate (NAND) arrays (know as multi-level flash memory). Also, the invention relates to a method for the fabrication of a NVM semiconductor device having two-bits per cell. The invention impacts an NVM semiconductor device's “window of operation”, broadening the window which permits more effective use of two-bits per cell NVM semiconductor devices.
Multi-level, or multi-bit, flash memory cells provide a solution for increasing the amount of data that can be stored on a memory device without consuming more space. Whereas a single-bit cell can store only two states, “on” and “off” (typically labeled “0” and “1”), a cell having n bits and using binary encoding is capable of storing up 2n states. Thus, a two-bit cell may store data in four discrete states, “00”, “01”, “10” and “11” which is distinctly more efficient that the “0” or “1” state alone. FIG. 1A shows a typical two-bit cell, generally labeled 10. The cell 10 has symmetrical source/drain regions 14 and 16 in connection with a semiconductor well 30. The well 30 and a gate 26 are separated from a charge trapping layer 20 by oxide regions 18 and 22. In some embodiments oxide layer 22 is not included in the NVM structure, as in the case of the NVM cell 40 shown in FIG. 1B.
A limitation with two-bits per cell NVM semiconductor devices is a narrow “window of operation” that exists after the conventional programming of a two-bit cell. The window of operation is generally described as the difference in the threshold voltage (Vt) of a programmed cell bit as compared to the Vt of the un-programmed (erased) state. FIG. 1C illustrates the distribution of the un-programmed Vt of the right bit 36 of FIG. 1D as well as the distribution of the programmed Vt of the right bit 36 of FIG. 1D (not shown). As FIG. 1C indicates, the window of operation of 4V in this example is that difference between the highest Vt of the un-programmed state 1 and the lowest Vt of the programmed state 0. Voltage thresholds and techniques for programming the left and right bits of NVM semiconductors are discussed in U.S. Pat. No. 6,011,725 (Eitan), the contents of which is incorporated by reference herein. As a cell bit is programmed from an un-programmed state (a logic 1) to a programmed state (a logic 0) the threshold voltage increases for that bit.
The greater the difference in the un-programmed Vt from the programmed-Vt allows for a clearer distinction between the programmed and un-programmed cell states for one-bit cells or to describe the state of the right bit and/or the left bit for two-bit cells. A greater difference between Vt of the two bits in a two-bit cell also allows for a clearer discrimination among the four distinct programmed cell states referred to above. Greater differences between the programmed and un-programmed state Vt, in other words a larger operational window, can be accomplished by programming from a lower voltage threshold. The lower the Vt pre-programming, then greater discrimination will exist between the un-programmed state and the programmed state. Memory cells with a larger operation window have the advantage of tolerating more charge loss and read disturb and such cells have greater endurance, which refers to the cycling of the program and erase steps.
As indicated in FIG. 1C, the window of operation is also known as the second bit window of operation regarding a two-bit memory cell. The second bit window of operation is generally described as the effect on the Vt of one bit that is not undergoing a programming action by the programming of the other bit associated with the same cell (the target bit). In other words, as seen in FIGS. 1E and 1F, as the left bit of memory cell 10, like that of the NVM shown FIG. 1A, is programmed from its initial state with un-programmed Vt to its programmed state with a programmed Vt, the Vt of the right bit undergoes a “shift” in that, although it is not being programmed, the right bit Vt is adjusted higher anyway and, thus has a higher Vt for the same bit state that existed before the left bit was programmed. As FIG. 2 indicates, the lower the Vt of both the bit to be programmed (the target bit of the cell) and the non-programmed bit (non-target bit of the cell), then a lower Vt shift for the non-programmed bit will be induced as the programmed bit undergoes a larger Vt shift for programming purposes. As seen in FIG. 2, the N-type channel implantation of the present invention provides a programmed Vt that is lower than the programmed Vt of a cell like that of the memory cell 10 of FIG. 1A or memory cell 40 of FIG. 1B that has no N-type channel implantation.
The conventional memory structure of the memory cell 10 and 40 of FIGS. 1A and 1B includes a P-type substrate 12 with no N-type channel implanted in the well region 30. This requires a positive Vg bias be applied to the gate 26 in order to achieve the inversion layer and induce a channel in the well 30.
Programming (i.e. charge injection) in two-bit NVM cells is achieved by various conventional hot carrier injection methods such as channel hot electron injection (CHE), source side injection (SSI) or channel initiated secondary electron (CHISEL). Erasing (i.e. charge removal) in two-bit NVM cells is achieved by various conventional methods such as band-to-band hot hole tunneling (BTBHH).
It is desirable to begin programming of two-bit memory cells with a lower Vt so that there will be a larger widow between the Vt of the programmed state and Vt of the non-programmed state in that there is a smaller Vt shift imposed on the non-programmed bit as the other, target bit, is programmed. For the same reasons, it is also desirable to have a lower programmed Vt state for a bit in a two-bit cell as compared to the un-programmed or erased Vt of the same bit.